Piestrak, S.J.: search on Z-Library

The world's largest scientific articles store. 70,000,000+ articles for free.

Don't use scam websites

1

Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication

Piestrak, StanisÅaw J., Pillement, Sebastien, Sentieys, Olivier

Journal:

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

Year:

2010

Language:

english

File:

PDF, 326 KB

english, 2010

2

Design of Reverse Converters for the New RNS Moduli Set $\{2^{n}+1,2^{n}-1,2^{n},2^{n-1}+1\}$ ($n$ odd)

Patronik, Piotr, Piestrak, Stanislaw J.

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2014

Language:

english

File:

PDF, 3.78 MB

english, 2014

3

[IEEE 2011 IEEE International Symposium on Circuits and Systems (ISCAS) - Rio de Janeiro, Brazil (2011.05.15-2011.05.18)] 2011 IEEE International Symposium of Circuits and Systems (ISCAS) - Design of multi-residue generators using shared logic

Piestrak, Stanislaw J.

Year:

2011

Language:

english

File:

PDF, 289 KB

english, 2011

4

Self-checking design in Eastern Europe

Journal:

IEEE Design & Test of Computers

Year:

1996

Language:

english

File:

PDF, 1.65 MB

english, 1996

5

[IEEE 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010 - Paris, France (2010.05.30-2010.06.2)] Proceedings of 2010 IEEE International Symposium on Circuits and Systems - Design of cost-efficient multipliers modulo 2a−1

Piestrak, Stanislaw J.

Year:

2010

Language:

english

File:

PDF, 246 KB

english, 2010

6

[IEEE 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Lisbon, Portugal (2015.5.24-2015.5.27)] 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Fault-aware configurable logic block for reliable reconfigurable FPGAs

Basha, B. Chagun, Pillement, Sebastien, Piestrak, Stanislaw J.

Year:

2015

Language:

english

File:

PDF, 1.08 MB

english, 2015

7

Design of parallel fault-secure encoders for systematic cyclic block transmission codes

Houssein Jaber, Fabrice Monteiro, StanisŁaw J. Piestrak, Abbas Dandache

Journal:

Microelectronics Journal

Year:

2009

Language:

english

File:

PDF, 601 KB

english, 2009

8

Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters

Stanislaw J. Piestrak

Journal:

Journal of Electronic Testing

Year:

1998

Language:

english

File:

PDF, 118 KB

english, 1998

9

General design principles of totally self-checking code-disjoint inverter-free PLAs

Journal:

IEE Proceedings - Circuits Devices and Systems

Year:

2004

Language:

english

File:

PDF, 324 KB

english, 2004

10

Design of residue generators and multioperand adders modulo 3 built of multioutput threshold circuits

Journal:

IEE Proceedings - Computers and Digital Techniques

Year:

1994

Language:

english

File:

PDF, 500 KB

english, 1994

11

Design of Fast Self-Testing Checkers for a Class of Berger Codes

Journal:

IEEE Transactions on Computers

Year:

1987

Language:

english

File:

PDF, 1.18 MB

english, 1987

12

Designing fault-secure parallel encoders for systematic linear error correcting codes

Piestrak, S.J., Dandache, A., Monteiro, F.

Journal:

IEEE Transactions on Reliability

Year:

2003

Language:

english

File:

PDF, 674 KB

english, 2003

13

Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication"

Piestrak, S.J., Pillement, S., Sentieys, O.

Journal:

IEEE Communications Letters

Year:

2010

Language:

english

File:

PDF, 181 KB

english, 2010

14

Comments on "Novel totally self-checking Berger checker designs based on generalized Berger code partitioning

Journal:

IEEE Transactions on Computers

Year:

2002

Language:

english

File:

PDF, 213 KB

english, 2002

15

Design of residue generators and multioperand modular adders using carry-save adders

Journal:

IEEE Transactions on Computers

Year:

1994

Language:

english

File:

PDF, 955 KB

english, 1994

16

The minimal test set for multioutput threshold circuits implemented as sorting networks

Journal:

IEEE Transactions on Computers

Year:

1993

Language:

english

File:

PDF, 1.14 MB

english, 1993

17

Design of self-testing checkers for Borden codes

Journal:

IEEE Transactions on Computers

Year:

1996

Language:

english

File:

PDF, 987 KB

english, 1996

18

Design of high-speed and cost-effective self-testing checkers for low-cost arithmetic codes

Journal:

IEEE Transactions on Computers

Year:

1990

Language:

english

File:

PDF, 1.26 MB

english, 1990

19

Design method of a class of embedded combinational self-testing checkers for two-rail codes

Journal:

IEEE Transactions on Computers

Year:

2002

Language:

english

File:

PDF, 150 KB

english, 2002

20

Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor

Hung-Manh Pham,, Pillement, S., Piestrak, S. J.

Journal:

IEEE Transactions on Computers

Year:

2013

Language:

english

File:

PDF, 1.33 MB

english, 2013

21

[IEEE 2011 International Symposium on Low Power Electronics and Design (ISLPED) - Fukuoka, Japan (2011.08.1-2011.08.3)] IEEE/ACM International Symposium on Low Power Electronics and Design - Fast and energy-efficient constant-coefficient FIR filters using residue number system

Patronik, Piotr, Berezowski, Krzysztof, Piestrak, Stanislaw J., Biernat, Janusz, Shrivastava, Aviral

Year:

2011

Language:

english

File:

PDF, 357 KB

english, 2011

22

A high-speed realization of a residue to binary number system converter

Journal:

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

Year:

1995

Language:

english

File:

PDF, 333 KB

english, 1995

23

Private reliability environments for efficient fault-tolerance in CGRAs

Jafri, Syed M. A. H., Piestrak, Stanislaw J., Hemani, Ahmed, Paul, Kolin, Plosila, Juha, Tenhunen, Hannu

Journal:

Design Automation for Embedded Systems

Year:

2014

Language:

english

File:

PDF, 1.44 MB

english, 2014

24

Design of the coarse-grained reconfigurable architecture DART with on-line error detection

Jafri, S.M.A.H., Piestrak, S.J., Sentieys, O., Pillement, S.

Journal:

Microprocessors and Microsystems

Year:

2014

Language:

english

File:

PDF, 1.37 MB

english, 2014

25

Design of Reverse Converters for General RNS Moduli Sets $\{ 2^{k}, 2^{n}-1, 2^{n}+1, 2^{n+1}-1 \}$ and $\{ 2^{k}, 2^{n}-1, 2^{n}+1, 2^{n-1}-1 \}$ ($n$ even)

Patronik, Piotr, Piestrak, Stanislaw J.

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2014

Language:

english

File:

PDF, 3.53 MB

english, 2014

26

Design of minimal-level PLA self-testing checkers for m-out-of-n codes

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

1996

Language:

english

File:

PDF, 1.09 MB

english, 1996

27

[IEEE Comput. Soc Seventh International On-Line Testing Workshop. IOLTW 2001 - Taormina, Italy (9-11 July 2001)] Proceedings Seventh International On-Line Testing Workshop - On the design of self-testing checkers for modified Berger codes

Piestrak, S.J., Bakalis, D., Kavousianos, X.

Year:

2001

Language:

english

File:

PDF, 451 KB

english, 2001

28

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Design of fault-secure encoders for a class of systematic error correcting codes

Piestrak, S.J., Dandache, A., Monteiro, F.

Year:

2001

Language:

english

File:

PDF, 262 KB

english, 2001

29

[IEEE 2013 International Symposium on System-on-Chip (SoC) - Tampere, Finland (2013.10.23-2013.10.24)] 2013 International Symposium on System on Chip (SoC) - Implementation and evaluation of configuration scrubbing on CGRAs: A case study

Jafri, Syed. M. A. H., Piestrak, Stanislaw J., Hemani, Ahmed, Paul, Kolin, Plosila, Juha, Tenhunen, Hannu

Year:

2013

Language:

english

File:

PDF, 1.83 MB

english, 2013

30

[IEEE Comput. Soc. Press 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA (10-12 Oct. 1994)] Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors - Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem

Year:

1994

Language:

english

File:

PDF, 398 KB

english, 1994

31

[IEEE Comput. Soc Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems - San Deigo, CA, USA (30 March-2 April 1998)] Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems - Membership test logic for delay-insensitive codes

Year:

1998

Language:

english

File:

PDF, 226 KB

english, 1998

32

[IEEE 11th IEEE International On-Line Testing Symposium - French Riviera, France (2005.07.8-2005.07.8)] 11th IEEE International On-Line Testing Symposium - Modeling of transients caused by a laser attack on smart cards

Leroy, D., Piestrak, S.J., Monteiro, F., Dandache, A.

Year:

2005

Language:

english

File:

PDF, 147 KB

english, 2005

33

[IEEE Comput. Soc. Press 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA (10-12 Oct. 1994)] Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors - Design of TSC code-disjoint inverter-free PLA's for separable unordered codes

Year:

1994

Language:

english

File:

PDF, 409 KB

english, 1994

34

[IEEE Comput. Soc. Press Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers - Pasadena, CA, USA (27-30 June 1995)] Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers - Towards totally self-checking delay-insensitive systems

Piestrak, S.J., Nanya, T.

Year:

1995

Language:

english

File:

PDF, 999 KB

english, 1995

35

[IEEE 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD) - Lille, France (2010.09.1-2010.09.3)] 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools - On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels

Piestrak, Stanislaw J.

Year:

2010

Language:

english

File:

PDF, 252 KB

english, 2010

36

[IEEE Comput. Soc. Press 10th IEEE Symposium on Computer Arithmetic - Grenoble, France (26-28 June 1991)] [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic - Design of residue generators and multioperand modular adders using carry-save adders

Year:

1991

Language:

english

File:

PDF, 770 KB

english, 1991

37

[IEEE Comput. Soc 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Paris, France (20-22 Oct. 1997)] 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes

Year:

1997

Language:

english

File:

PDF, 506 KB

english, 1997

38

[IEEE Comput. Soc 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002 - Vancouver, BC, Canada (6-8 Nov. 2002)] 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. - Feasibility study of designing TSC sequential circuits with 100% fault coverage

Year:

2002

Language:

english

File:

PDF, 859 KB

english, 2002

39

[IEEE Comput. Soc. Press IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA (14-16 Oct. 1991)] [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors - Design of a self-testing checker for Borden code

Year:

1991

Language:

english

File:

PDF, 375 KB

english, 1991

40

[IEEE Comput. Soc. Press [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium - Newcastle Upon Tyne, UK (26-28 June 1990)] [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium - The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes

Year:

1990

File:

PDF, 575 KB

1990

41

[IEEE 2014 17th Euromicro Conference on Digital System Design (DSD) - Verona, Italy (2014.8.27-2014.8.29)] 2014 17th Euromicro Conference on Digital System Design - Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes

Piestrak, Stanislaw J., Patronik, Piotr

Year:

2014

Language:

english

File:

PDF, 393 KB

english, 2014

42

[IEEE Systems (DDECS) - Cottbus, Germany (2011.04.13-2011.04.15)] 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - Error recovery technique for coarse-grained reconfigurable architectures

Azeem, Muhammad Moazam, Piestrak, Stanislaw J., Sentieys, Olivier, Pillement, Sebastien

Year:

2011

Language:

english

File:

PDF, 594 KB

english, 2011

43

[IEEE 13th IEEE International On-Line Testing Symposium (IOLTS 2007) - Crete, Greece (2007.07.8-2007.07.11)] 13th IEEE International On-Line Testing Symposium (IOLTS 2007) - Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes

Monteiro, Fabrice, Piestrak, Stanislaw J., Jaber, Houssein, Dandache, Abbas

Year:

2007

Language:

english

File:

PDF, 279 KB

english, 2007

44

[IEEE 2010 11th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2010.03.22-2010.03.24)] 2010 11th International Symposium on Quality Electronic Design (ISQED) - Design of a fault-tolerant coarse-grained

Jafri, Syed M. A. H., Piestrak, Stanislaw J., Sentieys, Olivier, Pillement, Sebastien

Year:

2010

Language:

english

File:

PDF, 224 KB

english, 2010

45

[IEEE Comput. Soc. Press 1993 IEEE 2nd Asian Test Symposium (ATS) - Beijing, China (16-18 Nov. 1993)] Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) - General design principles of self-testing code-disjoint PLAs

Year:

1993

Language:

english

File:

PDF, 663 KB

english, 1993

46

[IEEE 2013 Euromicro Conference on Digital System Design (DSD) - Los Alamitos, CA, USA (2013.09.4-2013.09.6)] 2013 Euromicro Conference on Digital System Design - Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs

Jafri, Syed M.A.H., Piestrak, Stanislaw J., Paul, Kolin, Hemani, Ahmed, Plosila, Juha, Tenhunen, Hannu

Year:

2013

Language:

english

File:

PDF, 372 KB

english, 2013

47

A note on RNS architectures for the implementation of the diagonal function

Piestrak, Stanisław J.

Journal:

Information Processing Letters

Year:

2015

Language:

english

File:

PDF, 276 KB

english, 2015

48

Design of squarers modulo A with low-level pipelining

Journal:

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

Year:

2002

Language:

english

File:

PDF, 415 KB

english, 2002

49

General design of area-efficient PLA self-testing checkers for 1-out-of-n codes

PIESTRAK, STANISLAW J.

Journal:

International Journal of Electronics

Year:

1994

Language:

english

File:

PDF, 283 KB

english, 1994

50

Design of fast self-testing checkers for m-out-of-2m and m-out-of-(2m ± 1) codes

PIESTRAK, STANISLAW J.

Journal:

International Journal of Electronics

Year:

1993

Language:

english

File:

PDF, 391 KB

english, 1993